1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device.
2. Description of the Related Art
A memory cell of a nonvolatile semiconductor memory device (for example, EEPROM) is usually formed with a structure of a charge accumulation layer and a control gate stacked on a semiconductor substrate. A threshold voltage of the memory cell differs for a state in which a charge is injected into the charge accumulation layer and released from the charge accumulation layer, and the threshold voltage is taken as data. The injection and release of charge is effected by the likes of a tunneling current that flows through a tunnel insulator formed between the charge accumulation layer and the semiconductor substrate.
Comparing types of EEPROM, a NAND type EEPROM (JP 03-295098 A) formed by serially connecting a plurality of memory cells may be formed with fewer select transistors than a NOR type EEPROM thus enabling attainment of high density. The NAND type EEPROM adopts a configuration in which a plurality of memory cell transistors are serially connected, a select transistor is provided at both ends of the serially connected memory cell transistors, and memory strings, in each of which a bit line contact and a source line contact are further connected to the select transistors, are disposed in an array.
In addition, n+ diffusion regions are formed in the semiconductor substrate to which the bit line contact and the source line contact are connected, and a depth of these n+ diffusion regions is usually identical.
Furthermore, it is widely known that a source line contact in a NAND type EEPROM is not individually formed for each of a plurality of memory strings but is commonly connected to the plurality of memory strings, and that a reduction in power consumption is achieved by keeping a resistance of the source line contact low.
However, when forming a contact hole for the source line contact with this method, etching sometimes progresses as far as the device isolation insulator adjacent to the semiconductor substrate. There is a problem that, for example, if etching of the device isolation insulator is effected deeply into a surface of the semiconductor substrate and the source line contact is formed there, a p-type well in the semiconductor substrate and the source line contact may end up short circuiting, which causes a large amount of junction leakage and deterioration in junction breakdown voltage, and consequently defective operation may occur.
Consequently, with conventional technology it has been difficult to provide a NAND type EEPROM that is formed without generating a large amount of junction leakage and worsening junction breakdown voltage.